H8SXSLASH1663R datasheet(330/1504 Pages) RENESAS

330 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 298 of 1468

REJ09B0412-0200

9.10.12

Refresh Control

This LSI includes a DRAM refresh control function. The refresh method is the CAS before RAS

(CBR) refresh. Self-refresh cycles can be performed in software standby mode.

The refresh control function is enabled when area 2 is specified as the DRAM space by the

DRAME and DTYPE bits in DRAMCR.

(1)

CAS before RAS (CBR) Refresh Mode

Set the RFSHE bit in REFCR to 1 to select the CBR refresh mode.

A CBR refresh cycle is performed when the value set in RTCOR matches the RTCNT value

(compare match). RTCNT is an up-counter operated on the input clock specified by bits RTCK2

to RTCK0 in REFCR. RTCNT is initialized upon the compare match and restarts to count up with

H'00. Accordingly, a CBR refresh cycle is repeated at intervals specified by bits RTCK2 to

RTCK0 in RTCOR. Set the bits so that the required refresh intervals of the DRAM must be

satisfied.

Since setting bits RTCK2 to RTCK0 starts RTCNT to count up, set RTCNT and RTCOR before

setting bits RTCK2 to RTCK0. When changing RTCNT and RTCOR, the counting operation

should be halted. When changing bits RTCK2 to RTCK0, change them only after disabling

external access and bus release by the EXDMAC, and if the write data buffer function is in use,

disabling the write data buffer function and reading the external space.

The external space cannot be accessed in CBR refresh mode.

Figure 9.52 shows RTCNT operation, figure 9.53 shows compare match timing, and figure 9.54

shows CBR refresh timing. Table 9.23 lists the pin states during a CBR refresh cycle.

RTCOR

H'00

Refresh request

RTCNT

Figure 9.52 RTCNT Operation

H8SX/1663R Datenblatt(PDF) 330 Page - Renesas Technology Corp