H8SXSLASH1663R datasheet(327/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 295 of 1468

REJ09B0412-0200

(2)

RAS Down Mode and RAS Up Mode

Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other

spaces may be accessed. The

RAS signal can be held low during other space accesses. The fast-

page mode access can be resumed (burst access) when the same row address in the DRAM space

is accessed.

(a)

RAS Down Mode

Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode.

The RCDM bit is enabled only when the BE bit is set to 1.

The fast-page mode access (burst access) is resumed when the row addresses of the current cycle

and previous cycle are the same. While other spaces are accessed when the DRAM space access is

halted, the

RAS signal must be low. Figure 9.50 shows a timing example of RAS down mode.

The

RAS signal goes high under the following conditions.

• When a refresh cycle is performed during RAS down mode

• When a self-refresh is performed

• When a transition to software standby mode is made

• When the external bus requested by the BREQ signal is released

• When either the RCDM or BE bit is cleared to 0

If a transition to the all-module clock-stop mode is made during RAS down mode, clocks are

stopped with the

RAS signal driven low. To make a transition with the RAS signal driven high,

clear the RCDM bit to 0 before execution of the SLEEP instruction.

Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see

section 27, Clock Pulse Generator.

H8SX/1663R Datenblatt(PDF) 327 Page - Renesas Technology Corp