H8SXSLASH1663R datasheet(340/1504 Pages) RENESAS

340 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 308 of 1468

REJ09B0412-0200

9.11.4

I/O Pins Used for DRAM Interface

Table 9.26 shows the pins used for the SDRAM interface.

Since a

CS pin functions as an input after a reset, set the bit in PFCR to 1 to output the CS signal.

For details, see section 13, I/O Ports.

To enable the SDRAM interface, select the appropriate MCU operating mode. For details, see

section 3, MCU Operating Modes.

Table 9.26

I/O Pins for SDRAM Interface

DRAM

Selected

Name

I/O

Function

RAS

Row address

strobe

Output

Row address strobe when the SDRAM

space is specified as area 2

CAS

Column address

strobe

Output

Column address strobe when the

SDRAM space is specified as area 2

Write enable

Output

Write enable signal for accessing the

SDRAM interface

OE/CKE

CKE

Clock enable

Output

Clock enable signal when the SDRAM

space is specified as area 2.

LLCAS/

DQMLU

Lower-upper data

mask enable

Output

Upper data mask enable when the 16-

bit SDRAM space is accessed

LLCAS/

DQMLL

Lower-lower data

mask enable

Output

• Lower data mask enable when the

16-bit SDRAM space is accessed

• Data mask enable when the 8-bit

SDRAM is accessed

A17 to A0

Address pin

Output

Multiplexed row/column-address output

D15 to D0

Data pin

Input/

output

Data input/output pin

PB7

SDRAM

Clock

Output

SDRAM clock

CS2

Chip select

Output

Strobe signal indicating that SDRAM is

selected

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