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H8SX/1663R Datenblatt(PDF) 343 Page - Renesas Technology Corp

Teilenummer H8SX/1663R
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
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H8SX/1663R Datenblatt(HTML) 343 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 311 of 1468
REJ09B0412-0200
9.11.6
CAS Latency Control
The CAS latency is controlled by bits W21 and W20 in WTCRB. Table 9.27 lists the setting and
CAS latency. CAS latency control cycles (Tcl) are inserted in a read cycle according to the W21
and W20 settings. WTCRB can be specified regardless of bit AST2 in ASTCR.
Figure 9.62 shows a timing example when SDRAM with a CAS latency of 3 is in use.
Bits W21 and W20 is initialized to B'11.
Table 9.27
CAS Latency Setting
W21
W20
Description
Number of CAS
Latency Cycles
0
0
Setting prohibited
1
SDRAM with CAS latency of 2 is in use
1
1
0
SDRAM with CAS latency of 3 is in use
2
1
SDRAM with CAS latency of 4 is in use
3



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