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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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H8SX/1663R Datenblatt(PDF) 387 Page - Renesas Technology Corp |
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H8SX/1663R Datenblatt(HTML) 387 Page - Renesas Technology Corp |
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387 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 355 of 1468 REJ09B0412-0200 (7) Idle Cycle for Accessing to DRAM/SDRAM Space In the following read cycles, when the DRAM/SDRAM space is accessed in a full access, the Tp and Tr cycles are also counted as idle cycles. Figures 9.99 and 9.100 show timing examples of full accesses to the DRAM/SDRAM space when four idle cycles are inserted. When accessing the DRAM/SDRAM space, the Ti cycles are inserted so that the sum of the numbers of Tp (precharge), Tr (row address output), and Ti cycles satisfies the specified number of idle cycles. The Ti cycles are inserted before the column address output cycle. While the SDRAM space is accessed in a full access, the CS2 signal is driven low even in an idle cycle. The idle cycle insertion is enabled even in a fast-page access in RAS down mode. The specified number of idle cycles is inserted. Figure 9.101 shows a timing example of the idle cycle insertion in RAS down mode. B φ Address bus RD RAS LLCAS T 1 T 2 T 3 T r T p T i T c1 T i T c2 External space read DRAM space read Data bus Figure 9.99 Example of DRAM Full Access after External Read (CAST = 0) |
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