H8SXSLASH1663R datasheet(383/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

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Hersteller	RENESAS [Renesas Technology Corp]

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 351 of 1468

REJ09B0412-0200

(3)

Read after Write

If an external read occurs after an external write while bit IDLS2 in IDLCR is set to 1, idle cycles

specified by bits IDLCA1 and IDLCA0 are inserted at the start of the read cycle (n = 0 to 7).

Figure 9.95 shows an example of the operation in this case. In this example, bus cycle A is a CPU

write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted,

and a conflict occurs in bus cycle B between the CPU write data and read data from an SRAM

device. In (b), an idle cycle is inserted, and a data conflict is prevented.

Output floating

time is long.

Data conflict

Bus cycle A

Bus cycle B

Address bus

CS (area A)

CS (area B)

LLWR

Data bus

Bus cycle A

Bus cycle B

(a) No idle cycle inserted

(IDLS2 = 0)

(b) Idle cycle inserted

(IDLS2 = 1, IDLCA1 = 0, IDLCA0 = 0)

Figure 9.95 Example of Idle Cycle Operation (Read after Write)

H8SX/1663R Datenblatt(PDF) 383 Page - Renesas Technology Corp