H8SXSLASH1663R datasheet(446/1504 Pages) RENESAS

446 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 414 of 1468

REJ09B0412-0200

Figure 10.13 shows an example of timing in cycle stealing mode. The transfer conditions are as

follows:

• Address mode: Single address mode

• Sampling method of the DREQ signal: Low level detection

CPU

DMAC

CPU

DMAC

DREQ

Bus cycle

Bus released temporarily for the CPU

Figure 10.13 Example of Timing in Cycle Stealing Mode

(2)

Burst Access Mode

In burst mode, once it takes the bus, the DMAC continues a transfer without releasing the bus until

the transfer end condition is satisfied. Even if a transfer is requested from another channel having

priority, the transfer is not stopped once it is started. The DMAC releases the bus in the next cycle

after the transfer for the channel in burst mode is completed. This is similarly to operation in cycle

stealing mode. However, setting the IBCCS bit in BCR2 of the bus controller makes the DMAC

release the bus to pass the bus to another bus master.

In block transfer mode, the burst mode setting is ignored (operation is the same as that in burst

mode during one block of transfers). The DMAC is always operated in cycle stealing mode.

Clearing the DTE bit in DMDR stops a DMA transfer. A transfer requested before the DTE bit is

cleared to 0 by the DMAC is executed. When an interrupt by a transfer size error, a repeat size

end, or an extended repeat area overflow occurs, the DTE bit is cleared to 0 and the transfer ends.

Figure 10.14 shows an example of timing in burst mode.

CPU

DMAC

Bus cycle

No CPU cycle generated

Figure 10.14 Example of Timing in Burst Mode

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