H8SXSLASH1663R datasheet(474/1504 Pages) RENESAS

474 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 442 of 1468

REJ09B0412-0200

(4)

Activation Timing by

DREQ Low Level

Figure 10.37 shows an example of normal transfer mode activated by the

DREQ signal low level.

The

DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately

after the DTE bit write cycle.

When a low level of the

DREQ signal is detected while a transfer request by the DREQ signal is

enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer

request is cleared. Receiving the next transfer request resumes after completion of the single cycle

and then a low level of the

DREQ signal is detected. This operation is repeated until the transfer is

completed.

Request

Wait

Request

Min. of 3 cycles

Transfer source/

Transfer destination

Single

Bus

released

Bus

released

Bus

released

DMA single

cycle

DMA single

cycle

DREQ

Address bus

DMA

operation

Channel

[1]

[2]

[3]

[4]

[5]

[6]

[7]

Transfer request

enable resumed

Transfer request

enable resumed

[1]

After DMA transfer request is enabled, a low level of the

DREQ signal is detected at the rising edge of the Bφ signal and a transfer

request is held.

[2][5] The DMAC is activated and the transfer request is cleared.

[3][6] A DMA cycle is started.

[4][7] Transfer request enable is resumed after completion of the single cycle.

(A low level of the

DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)

Transfer source/

Transfer destination

Single

DACK

Duration of transfer

request disabled

Duration of transfer

request disabled

Figure 10.37 Example of Transfer in Single Address Mode Activated

DREQ Low Level

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