H8SXSLASH1663R datasheet(477/1504 Pages) RENESAS

477 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 445 of 1468

REJ09B0412-0200

(3)

Transfer End by Repeat Size End Interrupt

In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data

transfer while the RPTIE bit in DACR is set to 1, a repeat size end interrupt is requested. When

the interrupt is requested to complete DMA transfer, the DTE bit in DMDR is cleared to 0 and the

ESIF bit in DMDR is set to 1. Under this condition, setting the DTE bit to 1 resumes the transfer.

In block transfer mode, when the next transfer is requested after completion of a 1-block size data

transfer, a repeat size end interrupt can be requested.

(4)

Transfer End by Interrupt on Extended Repeat Area Overflow

When an overflow on the extended repeat area occurs while the extended repeat area is specified

and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area

overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE

bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1.

In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a

read cycle, the following write cycle is performed.

In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1-

block transfer, the remaining data is transferred. The transfer is not terminated by an extended

repeat area overflow interrupt unless the current transfer is complete.

(5)

Transfer End by Clearing DTE Bit in DMDR

When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current

DMA cycle and a DMA cycle in which the transfer request is accepted are completed.

In block transfer mode, a DMA transfer is completed after 1-block data is transferred.

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