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H8SX/1663R Datenblatt(PDF) 487 Page - Renesas Technology Corp |
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H8SX/1663R Datenblatt(HTML) 487 Page - Renesas Technology Corp |
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487 / 1504 page ![]() Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 455 of 1468 REJ09B0412-0200 Figure 11.1 shows a block diagram of the EXDMAC. EDREQn EDACKn ETENDn EDRAKn EDMDR_n EDACR_n EDOFR_n EDSAR_n EDDAR_n EDTCR_n EDBSR_n CLSBR1 CLSBR2 CLSBR0 CLSBR7 . . . External pins Control unit Interrupt request signals to CPU for individual channels Internal address bus Internal data bus Data buffer Address buffer Processor Processor Module data bus EDSAR_n: EDDAR_n: EDOFR_n: EDTCR_n: EDBSR_n: EDMDR_n: EDACR_n: CLSBR0 to CLSBR7: EXDMA source address register EXDMA destination address register EXDMA offset register EXDMA transfer count register EXDMA block size register EXDMA mode control register EXDMA address control register Cluster buffer registers 0 to 7 EDREQn: EDACKn: ETENDn: EDRAKn: (n: 0 to 3) EXDMA transfer request EXDMA transfer acknowledge EXDMA transfer end EDREQ acceptance acknowledge [Legend] Figure 11.1 Block Diagram of EXDMAC |
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