H8SXSLASH1663R datasheet(483/1504 Pages) RENESAS

483 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 451 of 1468

REJ09B0412-0200

TSIE bit

DMAC is activated in

transfer size error state

RPTIE bit

DMAC is activated

after BKSZ bits are

changed from 1 to 0

SARIE bit

Extended repeat area

overflow occurs in

source address

DARIE bit

Extended repeat area

overflow occurs in

destination address

DTIE bit

DTIF bit

Transfer end

interrupt

[Setting condition]

When DTCR becomes 0

and transfer ends

Setting condition is satisfied

ESIE bit

ESIF bit

Transfer escape

end interrupt

Figure 10.39 Interrupt and Interrupt Sources

Transfer end interrupt

handling routine

Consecutive transfer

processing

Registers are specified

DTE bit is set to 1

Interrupt handling routine

ends (RTE instruction

executed)

Transfer resume

processing end

Transfer resumed after

interrupt handling routine

DTIF and ESIF bits are

cleared to 0

Interrupt handling routine

ends

DTE bit is set to 1

Registers are specified

Transfer resume

processing end

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[1] Specify the values in the registers such as transfer counter and address register.

[2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or

ESIF bit in DMDR to 0 and an interrupt source is cleared.

[3] End the interrupt handling routine by the RTE instruction.

[4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit.

[5] Complete the interrupt handling routine and clear the interrupt mask.

[6] Specify the values in the registers such as transfer counter and address register.

[7] Set the DTE bit to 1 to resume DMA operation.

Figure 10.40 Procedure Example of Resuming Transfer by Clearing Interrupt Source

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