H8SXSLASH1663R datasheet(499/1504 Pages) RENESAS

499 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 467 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

value

R/W

Description

EDACKE

R/W

EDACK Pin Output Enable

In single address mode, enables or disables output

from the

EDACK pin. In dual address mode, the

specification by this bit is ignored.

EDACK pin output disabled

EDACK pin output enabled

ETENDE

R/W

ETEND Pin Output Enable

Enables or disables output from the

ETEND pin.

ETEND pin output disabled

ETEND pin output enabled

EDRAKE

R/W

EDRAK Pin Output Enable

Enables or disables output from the

EDRAK pin.

EDRAK pin output disabled

EDRAK pin output enabled

EDREQS

R/W

EDREQ Select

Selects whether a low level or the falling edge of the

EDREQ signal used in external request mode is

detected.

0: Low-level detection

1: Falling edge detection (the first transfer is detected

on a low level after a transfer is enabled.)

NRD

R/W

Next Request Delay

Selects the timing of the next transfer request to be

accepted.

0: Next transfer request starts to be accepted after

transfer of the bus cycle in progress ends.

1: Next transfer request starts to be accepted after one

cycle of B

φ from the completion of the bus cycle in

progress.

25, 24



All 0

Reserved

They are always read as 0 and cannot be modified.

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