H8SXSLASH1663R datasheet(496/1504 Pages) RENESAS

496 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 464 of 1468

REJ09B0412-0200

Table 11.2

Data Access Size, Enable Bit, and Allowable Size

Mode

Data

Access Size

BKSZH

enable bit

BKSZ

enable bit

Allowable size (in bytes)

Byte

1 to 65,536

Word

2 to 131,072

Repeat transfer mode

Block transfer mode

Longword

31 to 16

15 to 0

4 to 262,144

Byte

20 to 16

4 to 0

1 to 32

Word

19 to 16

3 to 0

2 to 32

Cluster transfer mode

Longword

18 to 16

2 to 0

4 to 32

11.3.6

EXDMA Mode Control Register (EDMDR)

EDMDR controls EXDMAC operations.

• EDMDR_0

DTE

R/W

EDACKE

R/W

ETENDE

R/W

EDRAKE

R/W

EDREQS

R/W



NRD

R/W



Bit

Bit Name

Initial Value

R/W

ACT



ERRF

R/(W)*

DTIF

R/(W)*



ESIF

R/(W)*

Bit

Bit Name

Initial Value

R/W

DTSZ1

R/W

DTSZ0

R/W

MDS1

R/W

MDS0

R/W

TSEIE

R/W

DTIE

R/W



ESIE

R/W

Bit

Bit Name

Initial Value

R/W

DTF1

R/W

DTF0

R/W



R/W



EDMAP0

R/W

EDMAP2

R/W

EDMAP1

R/W

Bit

Bit Name

Initial Value

R/W

Note: *

Only 0 can be written to this bit after having been read as 1, to clear the flag.

H8SX/1663R Datenblatt(PDF) 496 Page - Renesas Technology Corp

H8SX/1663R Datenblatt(HTML) 496 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL