H8SXSLASH1663R datasheet(515/1504 Pages) RENESAS

515 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 483 of 1468

REJ09B0412-0200

Transfer

Address T

Address B

Address update setting

The source address incremented

The destination adderss is fixed

Address T

Figure 11.3 Dual Address Mode Operation

(2)

Single Address Mode

In single address mode, the

EDACK pin is used instead of EDSAR or EDDAR to transfer data

directly between an external device and external memory. One transfer operation is executed in

one bus cycle.

In this mode, the data bus width must be the same as the data access size. For details on the data

bus width, see section 9, Bus Controller (BSC).

In this mode, the EXDMAC accesses the transfer source or transfer destination external device by

outputting the strobe signal (

EDACK) for the external device with DACK, and at the same time

accesses the other external device in the transfer by outputting an address. In this way, EXDMA

transfer can be executed in one bus cycle. In the example of transfer between external memory and

an external device with

DACK shown in figure 11.4, data is output to the data bus by the external

device and written to external memory in the same bus cycle.

The transfer direction, that is whether the external device with

DACK is the transfer source or

transfer destination, can be specified with the DIRS bit in EDACR. Transfer is performed from the

external memory (EDSAR) to the external device with

DACK when DIRS = 0, and from the

external device with

DACK to the external memory (EDDAR) when DIRS = 1. The setting in the

source or destination address register not used in the transfer is ignored.

The

EDACK pin output is valid by the setting of EDACKE bit in EDMDR when single address

mode is selected. The

EDACK pin output is active-low.

ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND

is output for one bus cycle. When an idle cycle is inserted before the bus cycle, the

ETEND signal

is also output in the idle cycle.

Figure 11.5 shows an example of the timing in single address mode and figure 11.6 shows the

single address mode operation.

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