H8SXSLASH1663R datasheet(519/1504 Pages) RENESAS

519 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 487 of 1468

REJ09B0412-0200

Transfer

Address T

Address B

Operation with the repeat area

specified on the source address side

Total transfer

size (EDTCR)

Repeat size

(BKSZH

data access size)

Figure 11.9 Repeat Transfer Mode Operation

(3)

Block Transfer Mode

In block transfer mode, transfer of one block size unit is processed in response to one transfer

request. The total transfer size of up to 4 Gbytes can be set by EDTCR. The block size of up to 64

kbytes

× data access size can be set by EDBSR.

A transfer request from another channel is held pending during one block transfer. When one-

block transfer is completed, the bus mastership is released for another bus master.

A block area can be specified by the ARS1 or ARS0 bit in EDACR on the source or destination

address side. The address specified for the block area is restored to the transfer start address each

time one-block transfer completes. When no repeat area is specified on the source and destination

address sides, the address is not restored to the transfer start address and the operation proceeds to

the next sequence. A repeat size end interrupt can be generated.

The

ETEND signal is output for each block transfer in the EXDMA transfer cycle in which the

block ends. The

EDRAK signal is output once for one transfer request (for transfer of one block).

Caution is required when setting the extended repeat area overflow interrupt in block transfer

mode. For details, see section 11.5.5, Extended Repeat Area Function.

H8SX/1663R Datenblatt(PDF) 519 Page - Renesas Technology Corp