H8SXSLASH1663R datasheet(576/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 544 of 1468

REJ09B0412-0200

(2)

External Request/Cluster Transfer Mode/Cycle Steal Mode

With external requests, a cluster-size transfer is performed continuously. The start timing of the

next cluster transfer is the same as for normal transfer mode.

If a transfer request is generated for another channel, an EXDMA cycle for the other channel is

generated before the next cluster transfer.

The cluster transfer mode (read address mode and write address mode) can not be used with the

cluster transfer mode (dual address mode) among more than one channel at the same time. When

using the cluster transfer mode (read address mode and write address mode), do not set the cluster

transfer mode for another channel.

The

EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The

same applies to transfer request acceptance and transfer start timing.

Figures 11.67 to 11.69 show operation timing examples for various conditions.

H8SX/1663R Datenblatt(PDF) 576 Page - Renesas Technology Corp