H8SXSLASH1663R datasheet(572/1504 Pages) RENESAS

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Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 540 of 1468

REJ09B0412-0200

11.6.5

Operation Timing in Cluster Transfer Mode

This section describes examples of operation timing in cluster transfer mode. The CPU external

bus cycle is shown as an example of conflict with another bus master.

(1)

Auto-Request/Cluster Transfer Mode/Cycle Steal Mode

With auto-request (in cycle steal mode), when the DTE bit is set to 1 in EDMDR, a continuous

EXDMA transfer cycle is started a minimum of three cycles later. If there is a transfer request for

another channel of higher priority, the transfer request by the original channel is held pending, and

transfer is performed on the higher-priority channel from the next transfer. Transfer on the original

channel is resumed on completion of the higher-priority channel transfer.

The cluster transfer mode (read address mode and write address mode) can not be used with the

cluster transfer mode (dual address mode) among more than one channel at the same time. When

using the cluster transfer mode (read address mode and write address mode), do not set the cluster

transfer mode for another channel.

Figures 11.64 to 11.66 show operation timing examples for various conditions.

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