H8SXSLASH1663R datasheet(597/1504 Pages) RENESAS

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Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 565 of 1468

REJ09B0412-0200

12.2.4

DTC Destination Address Register (DAR)

DAR is a 32-bit register that designates the destination address of data to be transferred by the

DTC.

In full address mode, 32 bits of DAR are valid. In short address mode, the lower 24 bits of DAR is

valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of

bit 23.

If a word or longword access is performed while an odd address is specified in DAR or if a

longword access is performed while address 4n + 2 is specified in DAR, the bus cycle is divided

into multiple cycles to transfer data. For details, see section 12.5.1, Bus Cycle Division.

DAR cannot be accessed directly from the CPU.

12.2.5

DTC Transfer Count Register A (CRA)

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is

decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the

activation source is cleared and then an interrupt is requested to the CPU when the count reaches

H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536

when CRA = H'0000.

In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower

eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit

transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the

contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when

CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL =

H'00.

In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower

eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size

counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte

(word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the

count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01,

255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or

longwords) when CRAH = CRAL =H'00.

CRA cannot be accessed directly from the CPU.

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