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H8SX/1663R Datenblatt(PDF) 595 Page - Renesas Technology Corp

Teilenummer H8SX/1663R
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datenblatt(HTML) 595 Page - Renesas Technology Corp

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Section 12 Data Transfer Controller (DTC)
Rev. 2.00 Sep. 24, 2008 Page 563 of 1468
REJ09B0412-0200
12.2.2
DTC Mode Register B (MRB)
MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU.
Bit
Bit Name
Initial Value
R/W
7
CHNE
Undefined
6
CHNS
Undefined
5
DISEL
Undefined
4
DTS
Undefined
3
DM1
Undefined
2
DM0
Undefined
1
Undefined
0
Undefined
Bit
Bit Name
Initial
Value
R/W
Description
7
CHNE
Undefined
DTC Chain Transfer Enable
Specifies the chain transfer. For details, see section
12.5.7, Chain Transfer. The chain transfer condition is
selected by the CHNS bit.
0: Disables the chain transfer
1: Enables the chain transfer
6
CHNS
Undefined
DTC Chain Transfer Select
Specifies the chain transfer condition. If the following
transfer is a chain transfer, the completion check of the
specified transfer count is not performed and activation
source flag or DTCER is not cleared.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
5
DISEL
Undefined
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends. When
this bit is set to 0, a CPU interrupt request is only
generated when the specified number of data transfer
ends.
4
DTS
Undefined
DTC Transfer Mode Select
Specifies either the source or destination as repeat or
block area during repeat or block transfer mode.
0: Specifies the destination as repeat or block area
1: Specifies the source as repeat or block area



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