H8SXSLASH1663R datasheet(626/1504 Pages) RENESAS

626 / 1504 page

Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 594 of 1468

REJ09B0412-0200

12.9.9

Points for Caution when Overwriting DTCER

When overwriting of the DTC-transfer enable register (DTCER) and the generation of an interrupt

that is a source for DTC activation are in competition, activation of the DTC and interrupt

exception processing by the CPU will both proceed at the same time. Depending on the conditions

at this time, doubling of interrupts may occur. If there is a possibility of competition between

overwriting of the DTCER and generation of an interrupt that is a source for DTC activation,

proceed with overwriting of the DTCER according to the relevant procedure given below.

END

In the case of

interrupt-control mode 0

Back-up the value of the CCR.

Set the interrupt-mask bit to 1

(corresponding bit = 1 in the CCR).

Overwrite the DTCER.

Dummy-read the DTCER.

Restore the original value of the

interrupt-mask bit.

In the case of

interrupt-control mode 2

Back-up the value of the EXR.

Set the interrupt-request masking level to 7

(in the EXR, I2, I1, I0 = b'111).

Overwrite the DTCER.

Dummy-read the DTCER.

Restore the original value of the

interrupt-request masking level.

Interrupts are

masked

Figure 12.17 Example of Procedures for Overwriting the DTCER

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