H8SXSLASH1663R datasheet(623/1504 Pages) RENESAS

623 / 1504 page

Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 591 of 1468

REJ09B0412-0200

1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source

address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0.

2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first

data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at

addresses H'200000 to H'21FFFF, prepare H'21 and H'20.

3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for re-

setting the transfer destination address for the first data transfer. Use the upper eight bits of

DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0.

If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.

4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter

for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits

of the transfer source address for the first data transfer to H'21. The lower 16 bits of the

transfer destination address of the first data transfer and the transfer counter are H'0000.

5. Next, execute the first data transfer the 65536 times specified for the first data transfer by

means of interrupts. When the transfer counter for the first data transfer reaches 0, the second

data transfer is started. Set the upper eight bits of the transfer source address for the first data

transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer

and the transfer counter are H'0000.

6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,

no interrupt request is sent to the CPU.

1st data transfer

information

2nd data transfer

information

Transfer information

located on the on-chip memory

Chain transfer

(counter = 0)

Input circuit

Input buffer

Upper 8 bits of DAR

Figure 12.16 Chain Transfer when Counter = 0

H8SX/1663R Datenblatt(PDF) 623 Page - Renesas Technology Corp