H8SXSLASH1663R datasheet(720/1504 Pages) RENESAS

720 / 1504 page

Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 688 of 1468

REJ09B0412-0200

Input/output pins

TIOCA3

TIOCB3

TIOCC3

TIOCD3

TIOCA4

TIOCB4

TIOCA5

TIOCB5

Clock input

φ/1

φ/4

φ/16

φ/64

φ/256

φ/1024

φ/4096

TCLKA

TCLKB

TCLKC

TCLKD

Input/output pins

TIOCA0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

TIOCB1

TIOCA2

TIOCB2

Interrupt request signals

Channel 3:

Channel 4:

Channel 5:

Interrupt request signals

Channel 0:

Channel 1:

Channel 2:

Internal data bus

A/D conversion start request signal

PPG output trigger signal

TGI3A

TGI3B

TGI3C

TGI3D

TCI3V

TGI4A

TGI4B

TCI4V

TCI4U

TGI5A

TGI5B

TCI5V

TCI5U

TGI0A

TGI0B

TGI0C

TGI0D

TCI0V

TGI1A

TGI1B

TCI1V

TCI1U

TGI2A

TGI2B

TCI2V

TCI2U

Channel 3:

Channel 4:

Channel 5:

Internal clock:

External clock:

Channel 0:

Channel 1:

Channel 2:

[Legend]

TSTR:

Timer start register

TSYR:

Timer synchronous register

TCR:

Timer control register

TMDR:

Timer mode register

TIOR (H, L): Timer I/O control registers (H, L)

TIER:

Timer interrupt enable register

TSR:

Timer status register

TGR (A, B, C, D): Timer general registers (A, B, C, D)

TCNT:

Timer counter

Figure 14.1 Block Diagram of TPU (Unit 0)

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