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H8SX/1663R Datenblatt(PDF) 724 Page - Renesas Technology Corp |
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H8SX/1663R Datenblatt(HTML) 724 Page - Renesas Technology Corp |
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724 / 1504 page ![]() Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Sep. 24, 2008 Page 692 of 1468 REJ09B0412-0200 14.3 Register Descriptions The TPU has the following registers in each channel. Registers in the unit 0 and unit 1 have the same functions except for the bit 7 in TIER, namely, the TTGE bit in unit 0 and a reserved bit in unit 1. This section gives explanations regarding unit 0. Unit 0: • Channel 0: Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0) • Channel 1: Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1) |
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