H8SXSLASH1663R datasheet(763/1504 Pages) RENESAS

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 731 of 1468

REJ09B0412-0200

(b)

Free-running count operation and periodic count operation

Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters.

When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count

operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000),

the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this

point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000.

Figure 14.4 illustrates free-running counter operation.

TCNT value

H'FFFF

H'0000

CST bit

TCFV

Time

Figure 14.4 Free-Running Counter Operation

When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant

channel performs periodic count operation. The TGR register for setting the period is designated

as an output compare register, and counter clearing by compare match is selected by means of bits

CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts count-up operation as

a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches

the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000.

If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt.

After a compare match, TCNT starts counting up again from H'0000.

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