H8SXSLASH1663R datasheet(761/1504 Pages) RENESAS

761 / 1504 page

Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 729 of 1468

REJ09B0412-0200

14.3.9

Timer Synchronous Register (TSYR)

TSYR selects independent operation or synchronous operation for the TCNT counters of channels

0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.



R/W



R/W

SYNC5

R/W

SYNC4

R/W

SYNC3

R/W

SYNC2

R/W

SYNC1

R/W

SYNC0

R/W

Bit

Bit Name

Initial Value

R/W

Bit

Bit Name

Initial

value

R/W

Description

7, 6



All 0

R/W

Reserved

The write value should always be 0.

SYNC5

SYNC4

SYNC3

SYNC2

SYNC1

SYNC0

R/W

Timer Synchronization 5 to 0

These bits select whether operation is independent of or

synchronized with other channels.

When synchronous operation is selected, synchronous

presetting of multiple channels, and synchronous clearing

through counter clearing on another channel are possible.

To set synchronous operation, the SYNC bits for at least

two channels must be set to 1. To set synchronous

clearing, in addition to the SYNC bit, the TCNT clearing

source must also be set by means of bits CCLR2 to

CCLR0 in TCR.

0: TCNT_5 to TCNT_0 operate independently (TCNT

presetting/clearing is unrelated to other channels)

1: TCNT_5 to TCNT_0 perform synchronous operation

(TCNT synchronous presetting/synchronous clearing

is possible)

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