H8SXSLASH1663R datasheet(769/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 737 of 1468

REJ09B0412-0200

(2)

Example of Synchronous Operation

Figure 14.12 shows an example of synchronous operation.

In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to

2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and

synchronous clearing has been set for the channel 1 and 2 counter clearing source.

Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this

time, synchronous presetting and synchronous clearing by TGRB_0 compare match are performed

for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle.

For details on PWM modes, see section 14.4.5, PWM Modes.

TCNT_0 to TCNT_2 values

H'0000

TIOCA_0

TIOCA_1

TGRB_0

Synchronous clearing by TGRB_0 compare match

TGRA_2

TGRA_1

TGRB_2

TGRA_0

TGRB_1

TIOCA_2

Time

Figure 14.12 Example of Synchronous Operation

H8SX/1663R Datenblatt(PDF) 769 Page - Renesas Technology Corp