H8SXSLASH1663R datasheet(770/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 738 of 1468

REJ09B0412-0200

14.4.3

Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer

registers.

Buffer operation differs depending on whether TGR has been designated as an input capture

Table 14.30 shows the register combinations used in buffer operation.

Table 14.30 Register Combinations in Buffer Operation

Channel

Timer General Register

Buffer Register

TGRA_0

TGRC_0

TGRB_0

TGRD_0

TGRA_3

TGRC_3

TGRB_3

TGRD_3

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is

transferred to the timer general register.

This operation is illustrated in figure 14.13.

Buffer register

Timer general

TCNT

Comparator

Compare match signal

Figure 14.13 Compare Match Buffer Operation

H8SX/1663R Datenblatt(PDF) 770 Page - Renesas Technology Corp