H8SXSLASH1663R datasheet(789/1504 Pages) RENESAS

789 / 1504 page

Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 757 of 1468

REJ09B0412-0200

Channel

Name

Interrupt Source

Interrupt

Flag

DTC

Activation

DMAC

Activation

TGI3A

TGRA_3 input capture/compare match

TGFA_3

Possible

TGI3B

TGRB_3 input capture/compare match

TGFB_3

Possible

Not possible

TGI3C

TGRC_3 input capture/compare match

TGFC_3

Possible

Not possible

TGI3D

TGRD_3 input capture/compare match

TGFD_3

Possible

Not possible

TCI3V

TCNT_3 overflow

TCFV_3

Not possible

TGI4A

TGRA_4 input capture/compare match

TGFA_4

Possible

TGI4B

TGRB_4 input capture/compare match

TGFB_4

Possible

Not possible

TCI4V

TCNT_4 overflow

TCFV_4

Not possible

TCI4U

TCNT_4 underflow

TCFU_4

Not possible

TGI5A

TGRA_5 input capture/compare match

TGFA_5

Possible

TGI5B

TGRB_5 input capture/compare match

TGFB_5

Possible

Not possible

TCI5V

TCNT_5 overflow

TCFV_5

Not possible

TCI5U

TCNT_5 underflow

TCFU_5

Not possible

Note:

This table shows the initial state immediately after a reset. The relative channel priority

levels can be changed by the interrupt controller.

(1)

Input Capture/Compare Match Interrupt

An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1

by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is

cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts,

four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

(2)

Overflow Interrupt

An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to

1 by the occurrence of a TCNT overflow on a channel. The interrupt request is cleared by clearing

the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel.

(3)

Underflow Interrupt

An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to

1 by the occurrence of a TCNT underflow on a channel. The interrupt request is cleared by

clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4,

and 5.

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