H8SXSLASH1663R datasheet(801/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 769 of 1468

REJ09B0412-0200

14.10.5

Conflict between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence

and TCNT is not incremented. Figure 14.48 shows the timing in this case.

TCNT input

clock

TCNT

Address

Write

TCNT write cycle

TCNT write data

TCNT address

Figure 14.48 Conflict between TCNT Write and Increment Operations

14.10.6

Conflict between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence

and the compare match signal is disabled. A compare match also does not occur when the same

value as before is written.

Figure 14.49 shows the timing in this case.

TGR

Compare match

signal

TCNT

+ 1

Address

Write

TGR address

TGR write cycle

Disabled

TGR write data

Figure 14.49 Conflict between TGR Write and Compare Match

H8SX/1663R Datenblatt(PDF) 801 Page - Renesas Technology Corp