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H8SX/1663R Datenblatt(PDF) 804 Page - Renesas Technology Corp

Teilenummer H8SX/1663R
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datenblatt(HTML) 804 Page - Renesas Technology Corp

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Section 14 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Sep. 24, 2008 Page 772 of 1468
REJ09B0412-0200
14.10.10 Conflict between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 14.53 shows the timing in this case.
TCNT
P
φ
Input capture
signal
Address
Buffer register
address
Write
T
1
T
2
Buffer register write cycle
N
N
TGR
Buffer register
M
M
Figure 14.53 Conflict between Buffer Register Write and Input Capture



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