H8SXSLASH1663R datasheet(806/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 774 of 1468

REJ09B0412-0200

14.10.13 Multiplexing of I/O Pins

In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin

with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input

pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not

be performed from a multiplexed pin.

14.10.14 PPG1 Setting when TPU1 Pin is Used

When the TPU1 pin is used, the NDER bit of the PPG1 pin multiplexed with the TPU1 pin should

be cleared to halt the output. For details, see section 13, I/O Ports.

14.10.15 Interrupts in the Module Stop State

If module stop state is entered when an interrupt has been requested, it will not be possible to clear

the CPU interrupt source, or the DTC or DMAC activation sources. Interrupts should therefore be

disabled before entering module stop state.

H8SX/1663R Datenblatt(PDF) 806 Page - Renesas Technology Corp