H8SXSLASH1663R datasheet(297/1504 Pages) RENESAS

297 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 265 of 1468

REJ09B0412-0200

9.8

Burst ROM Interface

In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst

ROM interfacing performed. The burst ROM interface enables ROM with page access capability

to be accessed at high speed.

Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in

BROMCR. Consecutive burst accesses of up to 32 words can be performed, according to the

setting of bits BSWDn1 and BSWDn0 (n = 0, 1) in BROMCR. From one to eight cycles can be

selected for burst access.

Settings can be made independently for area 0 and area 1.

In the burst ROM interface, the burst access covers only read accesses by the CPU and EXDMAC

cluster transfer. Other accesses are performed with the similar method to the basic bus interface.

9.8.1

Burst ROM Space Setting

Burst ROM interface can be specified for areas 0 and 1. Areas 0 and 1 can be specified as burst

ROM space by setting bits BSRMn (n = 0, 1) in BROMCR.

9.8.2

Data Bus

The bus width of the burst ROM space can be specified as 8-bit or 16-bit burst ROM interface

space according to the ABWHn and ABWLn bits (n = 0, 1) in ABWCR.

For the 8-bit bus width, data bus (D7 to D0) is valid. For the 16-bit bus width, data bus (D15 to

D0) is valid.

Access size and data alignment are the same as the basic bus interface. For details, see section

9.5.6, Endian and Data Alignment.

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