H8SXSLASH1663R datasheet(313/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 281 of 1468

REJ09B0412-0200

9.10.3

Data Bus

The data bus width of the DRAM space can be selected from 8 and 16 bits by bits ABWH2 and

ABWL2 in ABWCR. DRAM with 16-bit words can be connected directly to 16-bit bus width

space.

D7 to D0 are valid in 8-bit DRAM space, and D15 to D0 are valid in 16-bit DRAM space.

The data endian format can be selected by bit LE2 in ENDIANCR. For details on the access size

and alignment, see section 9.5.6, Endian and Data Alignment.

9.10.4

I/O Pins Used for DRAM Interface

Table 9.22 shows the pins used for the DRAM interface.

Table 9.22

I/O Pins for DRAM Interface

DRAM

Selected

Name

I/O

Function

Write enable

Output

Write enable signal for accessing the

DRAM interface

RAS

Row address

strobe

Output

Row address strobe when the DRAM

space is specified as area 2

LUCAS/

DQMLU

LUCAS

Lower-upper

column address

strobe

Output

• Lower-upper column address strobe

when the 32-bit DRAM space is

accessed

• Upper column address strobe when the

16-bit DRAM space is accessed

LLCAS/

DQMLL

LLCAS

Lower-lower

column address

strobe

Output

• Lower-lower column address strobe

when the 32-bit DRAM space is

accessed

• Lower column address strobe when the

16-bit DRAM space is accessed

Output enable

Output

Output enable signal when the DRAM

space is accessed

WAIT

Wait

Input

Wait request signal used when an external

address space is accessed

A17 to A0

Address pin

Output

Multiplexed address/data output pin

D15 to D0

Data pin

Input/

output

Data input/output pin

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