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H8SX/1663R Datenblatt(PDF) 315 Page - Renesas Technology Corp

Teilenummer H8SX/1663R
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datenblatt(HTML) 315 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 283 of 1468
REJ09B0412-0200
9.10.6
Controlling Column Address Output Cycle
The number of column address output cycles can be changed from two to three clock cycles by
setting the CAST bit in DRAMCR. Set the bit according to the DRAM to be used and the
frequency of this LSI so that the
CAS pulse width can be optimal.
Figure 9.39 shows a timing example when the number of column address output cycles is set to
three clock cycles.
T
p
T
r
T
c1
T
c2
T
c3
Address bus
Row address
Column address
B
φ
RAS
LUCAS
LLCAS
WE
OE (RD)
WE
OE (RD)
Data bus
High
High
Read
Write
Data bus
BS
RD/
WR
Figure 9.39 Access Timing Example of Column Address Output Cycles for 3 Clock Cycles
(RAST = 0)



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