H8SXSLASH1663R datasheet(319/1504 Pages) RENESAS

319 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 287 of 1468

REJ09B0412-0200

9.10.9

Wait Control

There are two methods of inserting wait cycles during a DRAM access cycle: program wait

insertion and pin wait insertion using the WAIT pin.

Wait cycles are inserted to extend the

CAS assertion period during a DRAM read cycle and to

ensure the write data setup time to the falling edge of the

CAS signal during a DRAM write cycle.

(1)

Program Wait Insertion

When bit AST2 in ASTCR is set to 1, zero to seven of wait cycles can automatically be inserted

between the Tc1 and Tc2 cycles. The number of wait cycles is selected by bits W22 to W20 in

WTCRB.

(2)

Pin Wait Insertion

When the WAITE bit in BCR1 is set to 1, and the AST2 bit in ASTCR is set to 1, setting the ICR

bit for the corresponding pin to 1 enables wait input by the

WAIT pin. When the DRAM space is

accessed in this state, a program wait (Tpw) is first inserted. If the

WAIT pin is low at the rising

edge of B

φ in the last Tc1 or Tpw cycle, another Ttw cycle is inserted until the WAIT pin is driven

high. For details on ICR, see section 13, I/O Ports.

Figure 9.43 shows an example of wait cycle insertion timing for 2-cycle column address output.

Figure 9.44 shows an example of wait cycle insertion timing for 3-cycle column address output.

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