H8SXSLASH1663R datasheet(324/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 292 of 1468

REJ09B0412-0200

RAS

UCAS

LCAS

A10

D15 to D0

RAS

LUCAS

LLCAS

RD (OE)

A11

A10

D15 to D0

This LSI

(Address shifted by 11 bits)

Two CAS signals used 64-Mbit DRAM

(4 Mwords

× 16 bits)

11-bit column address

Row address input:

A10 to A0

Column address input: A10 to A0

Figure 9.47 Example of Connection for Control with Two CAS Signals

9.10.11

Burst Access Operation

Besides an accessing method in which this LSI outputs a row address every time it accesses the

DRAM (called full access or normal access), some DRAMs have a fast-page mode function in

which fast speed access can be achieved by modifying only a column address with the same row

address output (burst access) when consecutive accesses are made to the same row address.

The fast-page mode (burst access) can be specified when the BE bit in DRAMCR is set to one,

(1)

Burst Access (Fast-Page Mode) Operation Timing

Figures 9.48 and 9.49 show operation timing of the fast-page mode.

When access cycles to the DRAM space are continued and the row addresses of the consecutive

two cycles are the same, output cycles of the CAS and column address signals follow. The row

address bits to be compared are decided by bits MXC1 and MXC0 in DRAMCR.

Wait cycles can be inserted during a burst access. The method and timing of the wait insertion are

the same as that of full access mode. For details, see section 9.10.9, Wait Control.

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