H8SXSLASH1663M datasheet(486/1504 Pages) RENESAS

486 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 454 of 1468

REJ09B0412-0200

Cluster transfer mode: One cluster data is transferred at a single transfer request

Up to 32-byte data can be set as cluster size

• Selection of extended repeat area function (to transfer data such as ring buffer data by fixing

the upper bit value in the transfer address register and repeating the address values in a

specified range)

For the extended repeat area, 1 bit (2 bytes) to 27 bits (128 Mbytes) can be set independently

for the transfer source or destination.

• Selection of address update methods: Increment/decrement by 1, 2 or 4, fixed, or offset

addition

When offset addition is used to update addresses, the mid-addresses can be skipped during data

transfer.

• Transfer of word or longword data to addresses beyond each data boundary

Data can be divided into an optimal data size (byte or word) according to addresses when

transferring data.

• Two kinds of interrupts requested to the CPU

Transfer end interrupt: Requested after the number of data set by the transfer counter has been

completely transferred

Transfer escape end interrupt: Requested when the remaining transfer size is smaller than the

size set for a single transfer request, after a repeat-size transfer is completed, or when an

extended repeat area overflow occurs.

• Acceptance of a transfer request can be reported to an external device via the EDRAK pin

(only for the EXDMAC).

• Operation of EXDMAC, connected to a dedicated bus, in parallel with a bus master such as the

CPU, DTC, or DMAC (only for the EXDMAC).

• Module stop state can be set.

H8SX/1663M Datenblatt(PDF) 486 Page - Renesas Technology Corp