H8SXSLASH1663M datasheet(273/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 241 of 1468

REJ09B0412-0200

9.5.6

Endian and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus

controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8)

or lower data bus (D7 to D0) is used according to the bus specifications for the area being

accessed (8-bit access space or 16-bit access space), the data size, and endian format when

accessing external address space.

(1)

8-Bit Access Space

With the 8-bit access space, the lower byte data bus (D7 to D0) is always used for access. The

amount of data that can be accessed at one time is one byte: a word access is performed as two

byte accesses, and a longword access, as four byte accesses.

Figures 9.11 and 9.12 illustrate data alignment control for the 8-bit access space. Figure 9.11

shows the data alignment when the data endian format is specified as big endian. Figure 9.12

shows the data alignment when the data endian format is specified as little endian.

Longword

Access

Address

Access

Count

Data

Size

Byte

Word

1st

2nd

1st

2nd

3rd

4th

Bus

Cycle

Data Size

Data bus

D15

D8 D7

LHWR/LUB

LLWR/LLB

Strobe signal

Figure 9.11 Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian)

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