SH7708 datasheet(362/633 Pages) RENESAS

362 / 633 page

344

13.2

13.2.1

Receive Shift Register (SCRSR)

The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into

SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one

byte has been received, it is automatically transferred to SCRDR. The CPU cannot read or write

SCRSR directly.

Bit:

Bit name:

R/W:

—

13.2.2

Receive Data Register (SCRDR)

The receive data register (SCRDR) stores serial receive data. The SCI completes the reception of

one byte of serial data by moving the received data from the receive shift register (SCRSR) into

SCRDR for storage. SCRSR is then ready to receive the next data. This double buffering allows

the SCI to receive data continuously.

The CPU can read but not write to SCRDR. SCRDR is initialized to H'00 by a reset and in standby

or module standby mode.

Bit:

Bit name:

Initial value:

R/W:

13.2.3

Transmit Shift Register (SCTSR)

The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the

transmit data register (SCTDR) into SCTSR, then transmits the data serially from the TxD pin,

LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit

data from SCTDR into SCTSR and starts transmitting again. If the TDRE bit in SCSSR is 1,

however, the SCI does not load the SCTDR contents into SCTSR. The CPU cannot read or write

to SCTSR directly.

Bit:

Bit name:

R/W:

—

SH7708 Datenblatt(PDF) 362 Page - Renesas Technology Corp