SH7708 datasheet(367/633 Pages) RENESAS

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Bit 5: TE

Description

Transmitter disabled

(Initial value)

The transmit data register empty bit (TDRE) in the serial status register

(SCSSR) is locked at 1.

Transmitter enabled

Serial transmission starts when the transmit data register empty (TDRE)

bit in the serial status register (SCSSR) is cleared to 0 after writing of

transmit data into SCTDR. Select the transmit format in SCSMR before

setting TE to 1.

Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.

Bit 4: RE

Description

Receiver disabled

(Initial value)

Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER,

ORER). These flags retain their previous values.

Receiver enabled

Serial reception starts when a start bit is detected in asynchronous

mode, or synchronous clock input is detected in synchronous mode.

Select the receive format in SCSMR before setting RE to 1.

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit

(MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is

ignored in synchronous mode or when the MP bit is cleared to 0.

Bit 3: MPIE

Description

Multiprocessor interrupts are disabled (normal receive operation).

(Initial value)

MPIE is cleared to 0 by writing 0 to it, or when the multiprocessor bit

(MPB) is set to 1 in receive data.

Multiprocessor interrupts are enabled.

Receive-data-full interrupt requests (RXI), receive-error interrupt

requests (ERI), and setting of the RDRF, FER, and ORER status flags

in the serial status register (SCSSR) are disabled until data with a

multiprocessor bit of 1 is received.

The SCI does not transfer receive data from SCRSR to SCRDR, does

not detect receive errors, and does not set the RDRF, FER, and ORER

flags in the serial status register (SCSSR). When it receives data that

includes MPB = 1, the SCSSR’s MPB flag is set to 1, and the SCI

automatically clears MPIE to 0, generates RXI and ERI interrupts (if the

TIE and RIE bits in SCSCR are set to 1), and allows the FER and

ORER bits to be set.

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