SH7708 datasheet(385/633 Pages) RENESAS

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Table 13.11 Serial Communication Formats (Asynchronous Mode)

SCSMR Bits

Serial Transmit/Receive Format and Frame Length

CHR PE

STOP

2345678

8-bit data

STOP

8-bit data

STOP STOP

8-bit data

STOP

8-bit data

STOP STOP

7-bit data

STOP

7-bit data

STOP STOP

7-bit data

STOP

7-bit data

STOP STOP

—

8-bit data

MPB

STOP

—

8-bit data

MPB

STOP STOP

—

7-bit data

MPB

STOP

—

7-bit data

MPB

STOP STOP

Legend

— :

Don’t care bits

Start bit

STOP: Stop bit

Parity bit

MPB:

Multiprocessor bit

Clock: An internal clock generated by the on-chip baud rate generator or an external clock input

from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected

by the C/

A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control

When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the

desired bit rate.

When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The

frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 13.3

so that the rising edge of the clock occurs at the center of each transmit data bit.

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