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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SH7708 Datenblatt(PDF) 414 Page - Renesas Technology Corp |
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SH7708 Datenblatt(HTML) 414 Page - Renesas Technology Corp |
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414 / 633 page  396 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 Base clock Receive data (RxD) Synchro- nization sampling timing Data sampling timing 8 clock cycles 16 clock cycles Start bit –7.5 clock cycles +7.5 clock cycles D0 D1 Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in the asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: M = 0.5 – 1 2N D – 0.5 N – (L – 0.5)F – (1 + F) × 100% Where: M = Receive margin (%) N = Ratio of clock frequency to bit rate (N = 16) D = Clock duty cycle (D = 0–1.0) L = Frame length (L = 9–12) F = Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as shown in equation 2. Equation 2: M = (0.5 – 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20–30%. |
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