| Datenblatt-Suchmaschine für elektronische Bauteile |
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SH7708 Datenblatt(PDF) 316 Page - Renesas Technology Corp |
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SH7708 Datenblatt(HTML) 316 Page - Renesas Technology Corp |
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316 / 633 page ![]() 298 In the case of consecutive word and byte accesses, or consecutive longword and byte accesses, in area 6, CE1B and CE2B are asserted simultaneously in the byte access. As a result, a byte write becomes a word-size write. In a byte read, the byte data at the specified address is read correctly. Use one of the following methods to avoid this problem. 1. Do not use area 6 PCMCIA. 2. Use an 8-bit bus width for area 6 PCMCIA. 3. If a 16-bit bus width is used for area 6 PCMCIA, do not perform byte-size write accesses. 4. In consecutive accesses a. and b. below a. Word access → byte access (write) b. Longword access → byte access (write) in which this problem arises, the problem can be avoided by performing a dummy read in a non-cacheable area as shown in (a') and (b') below. a'. Word access → dummy read → byte access (write) b'. Longword access → dummy read → byte access (write) 10.4.3 Self-Refreshing 1. Note the following concerning the SH7708 (not including the SH7708S and SH7708R). When DRAM is connected in both area 2 and area 3, if • self-refreshing is executed for the memory in only one of the areas, or • a value corresponding to the above condition is written to the MCR or DCR register as a program operation after setting execution of CBR refreshing for both areas, use the procedure shown in (a), (b), and (c) below. a. Make a setting so that refreshing is not performed for either area 2 or area 3 (clear the RFSH bit to 0 in both the MCR and DCR registers). b. Execute self-refreshing for one of the areas. c. Make a new setting so that auto-refreshing is executed for the area in which self-refreshing is not used. 2. Note the following concerning the SH7708 Series (SH7708, SH7708S, SH7708R). If the refresh mode bit (the RMODE bit in registers MCR and DCR) is to be changed while the refresh control bit (the RFSH bit in registers MCR and DCR) is set to 1, use the procedure shown in a. and b. below. a. Clear the refresh control bit to 0. b. When refreshing is not being performed, set the refresh control bit to 1 again and then change the refresh mode. |
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