SH7708 datasheet(330/633 Pages) RENESAS

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11.3

TMU Operation

11.3.1

Overview

Each of the three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register.

The TCNT counts down. The auto-reload function enables synchronized counting and counting by

external events. Channel 2 has an input capture function.

11.3.2

Basic Functions

Counter Operation: When the STR0–STR2 bits in the timer start register (TSTR) are set, the

corresponding timer counter (TCNT) starts counting. When a TCNT underflows (H'00000000

→

H'FFFFFFFF), the UNF flag of the corresponding timer control register (TCR) is set. At this time,

if the UNIE bit in TCR is 1, an interrupt request is sent to the CPU. Also at this time, the value is

copied from TCOR to TCNT and the down-count operation is continued.

The count operation is set as follows (figure 11.2):

1. Select the counter clock with the TPSC2–TPSC0 bits in the timer control register (TCR). If the

external clock is selected, set the TCLK pin to input mode with the TOCE bit in TOCR, and

select its edge with the CKEG1 and CKEG0 bits in TCR.

2. Use the UNIE bit in TCR to set whether to generate an interrupt when TCNT underflows.

3. When using the input capture function, set the ICPE bits in TCR, including the choice of

whether or not to use the interrupt function (channel 2 only).

4. Set a value in the timer constant register (TCOR) (the cycle is the set value plus 1).

5. Set the initial value in the timer counter (TCNT).

6. Set the STR bit in the timer start register (TSTR) to 1 to start operation.

SH7708 Datenblatt(PDF) 330 Page - Renesas Technology Corp