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CONNECTION WITH EXTERNAL DEVICES

3.1 Signals required for accessing external devices

7721 Group User’s Manual

3–2

3.1 Signals required for accessing external devices

The functions and operations of the signals which are required for accessing the external devices are

described below.

When connecting an external device that requires long access time, refer to sections “3.2 Software Wait,”

“3.3 Ready function,” and “3.4 Hold function,” as well as this section. When the external DRAM is

controlled by using DRAM controller, refer to “CHAPTER 14. DRAM CONTROLLER.”

3.1.1 Descriptions of signals

Figure 3.1.1 shows the pin configurations when the external data bus width is 16 bits and 8 bits.

(1)

External buses (A0–A7, A8/D8–A15/D15, A16/D0–A23/D7)

The external area is specified by the address (A0–A23) output.

The A8–A23 pins of the external address bus and the D0–D15 pins of the external data bus are

assigned to the same pins.

When the BYTE pin level, described later, is “L” (external data bus width is 16 bits), the A8/D8–

A15/D15 and A16/D0–A23/D7 pins perform address output and data input/output with time-sharing.

When the BYTE pin level is “H” (external data bus width is 8 bits), the A16/D0–A23/D7 pins perform

address output and data input/output with time-sharing, and the A8–A15 pins output the address.

(2)

External data bus width switching signal (BYTE pin level)

This signal is used to select the external data bus width from 8 bits and 16 bits. The width is 16 bits

when the level is “L,” and 8 bits when the level is “H.” Fix this signal to either “H” or “L” level. This

signal is valid only for the external area. (When accessing the internal area, the data bus width is

always 16 bits.)

(3)

Enable signal (E)

This signal becomes “L” level while reading or writing data from and to the data bus. (Refer to

“Table 3.1.1.”)

(4)

Read/Write signal (R/W)

This signal indicates the state of the data bus. This signal becomes “L” level while writing data to

the data bus. Table 3.1.1 lists the state of the data bus indicated with the E and R/W signals.

Table 3.1.1 State of data bus indicated with E and

R/W signals

R/W

State of data bus

Not used

Read data

Write data

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