M38043F7HKP datasheet(12/387 Pages) RENESAS

12 / 387 page

viii

3804 Group (Spec.H)

List of figures

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

Fig. 2.4.3 Structure of Serial I/O1 status register and Serial I/O3 status register ............. 2-48

Fig. 2.4.4 Structure of Serial I/O1 control register .................................................................. 2-49

Fig. 2.4.5 Structure of Serial I/O3 control register .................................................................. 2-50

Fig. 2.4.6 Structure of UART1 control register ........................................................................ 2-51

Fig. 2.4.7 Structure of UART3 control register ........................................................................ 2-51

Fig. 2.4.8 Structure of Baud rate generator 1 and Baud rate generator 3 ......................... 2-52

Fig. 2.4.9 Structure of Serial I/O2 control register .................................................................. 2-52

Fig. 2.4.10 Structure of Serial I/O2 register ............................................................................. 2-53

Fig. 2.4.11 Structure of Interrupt source selection register ................................................... 2-53

Fig. 2.4.12 Structure of Interrupt request register 1 ............................................................... 2-54

Fig. 2.4.13 Structure of Interrupt request register 2 ............................................................... 2-54

Fig. 2.4.14 Structure of Interrupt control register 1 ................................................................ 2-55

Fig. 2.4.15 Structure of Interrupt control register 2 ................................................................ 2-55

Fig. 2.4.16 Serial I/O connection examples (1) ....................................................................... 2-56

Fig. 2.4.17 Serial I/O connection examples (2) ....................................................................... 2-57

Fig. 2.4.18 Serial I/O transfer data format ............................................................................... 2-58

Fig. 2.4.19 Connection diagram ................................................................................................. 2-61

Fig. 2.4.20 Timing chart (using clock synchronous serial I/O) .............................................. 2-61

Fig. 2.4.21 Registers setting relevant to transmitting side ..................................................... 2-62

Fig. 2.4.22 Registers setting relevant to receiving side ......................................................... 2-63

Fig. 2.4.23 Control procedure of transmitting side .................................................................. 2-64

Fig. 2.4.24 Control procedure of receiving side ...................................................................... 2-65

Fig. 2.4.25 Connection diagrams ............................................................................................... 2-66

Fig. 2.4.26 Timing chart (serial I/O1) ........................................................................................ 2-66

Fig. 2.4.27 Registers setting relevant to serial I/O1 ............................................................... 2-67

Fig. 2.4.28 Setting of serial I/O1 transmission data ............................................................... 2-67

Fig. 2.4.29 Control procedure of serial I/O1 ............................................................................ 2-68

Fig. 2.4.30 Registers setting relevant to serial I/O2 ............................................................... 2-69

Fig. 2.4.31 Setting of serial I/O2 transmission data ............................................................... 2-69

Fig. 2.4.32 Control procedure of serial I/O2 ............................................................................ 2-70

Fig. 2.4.33 Connection diagram ................................................................................................. 2-71

Fig. 2.4.34 Timing chart .............................................................................................................. 2-72

Fig. 2.4.35 Relevant registers setting ....................................................................................... 2-72

Fig. 2.4.36 Control procedure of master unit ........................................................................... 2-73

Fig. 2.4.37 Control procedure of slave unit ............................................................................. 2-74

Fig. 2.4.38 Connection diagram (Communication using UART) ............................................ 2-75

Fig. 2.4.39 Timing chart (using UART) ..................................................................................... 2-75

Fig. 2.4.40 Registers setting relevant to transmitting side ..................................................... 2-77

Fig. 2.4.41 Registers setting relevant to receiving side ......................................................... 2-78

Fig. 2.4.42 Control procedure of transmitting side .................................................................. 2-79

Fig. 2.4.43 Control procedure of receiving side ...................................................................... 2-80

Fig. 2.4.44 Sequence of setting serial I/Oi (i = 1, 3) control register again ....................... 2-82

Fig. 2.5.1 Memory map of registers relevant to I2C-BUS interface ...................................... 2-84

Fig. 2.5.2 Structure of MISRG ................................................................................................... 2-85

Fig. 2.5.3 Structure of I2C data shift register ........................................................................... 2-85

Fig. 2.5.4 Structure of I2C special mode status register ........................................................ 2-86

Fig. 2.5.5 Structure of I2C status register ................................................................................. 2-87

Fig. 2.5.6 Structure of I2C control register ............................................................................... 2-88

Fig. 2.5.7 Structure of I2C clock control register ..................................................................... 2-89

Fig. 2.5.8 Structure of I2C START/STOP condition control register ..................................... 2-90

Fig. 2.5.9 Structure of I2C special mode control register ....................................................... 2-90

Fig. 2.5.10 Structure of I2C slave address register i (i = 0 to 2) ......................................... 2-91

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