TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M

LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS

SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999

8

POST OFFICE BOX 655303

converter

The CMOS threshold detector in the successive-approximation conversion system determines the value of

each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase

simultaneously. This action charges all of the capacitors to the input voltage.

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF –)

voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and

then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector

looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the

equivalent nodes of all the other capacitors on the ladder are switched to REF –. If the voltage at the summing

output register and the 512-weight capacitor is switched to REF –. If the voltage at the summing node is less

than the trip point of the threshold detector, a bit 1 is placed in the register and the 512-weight capacitor remains

connected to REF + through the remainder of the successive-approximation process. The process is repeated

for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.

With each step of the successive-approximation process, the initial charge is redistributed among the

capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.

SC

Threshold

Detector

Node 512

REF –

REF+

ST

512

VI

To Output

Latches

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

ST

REF+

REF –

ST

REF+

REF –

ST

1

1

2

4

8

128

256

REF –

Figure 1. Simplified Model of the Successive-Approximation System