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TDA7580 Datenblatt(PDF) 20 Page - STMicroelectronics |
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TDA7580 Datenblatt(HTML) 20 Page - STMicroelectronics |
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20 / 31 page ![]() TDA7580 20/31 INTER PROCESSOR TRANSPORT INTERFACE FOR ANTENNA DIVERSITY Figure 10. High Speed Synchronous Serial Interface - HS 3I Note TDSP = DSP master clock cycle time = 1/FDSP Timing Description Value Unit TDSP Internal DSP Clock Period (Typical 1/74.1MHz) tmbcc MBC minimum Clock Cycle 32*TDSP ns tmbco MBC active edge to master data out valid 4 ns tmbcs MBC active edge to master synch valid 4 ns tsdos Slave Data Out setup time 6 ns Master Bit Clock Master Data Out Master Synch Slave Data Out M2 M3 S0 S1 S2 S3 256 cycles of 74.1MHz tmbcc tmbco Master Synch Master Data Out Master Bit Clock Slave Data Out tmbcs tsdos |
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