AD9783-EBZ datasheet(19/36 Pages) AD

19 / 36 page

AD9780/AD9781/AD9783

Rev. A | Page 19 of 36

Bits[4:0], A4, A3, A2, A1, and A0, determine which register is

accessed during the data transfer of the communication cycle.

For multibyte transfers, this address is a starting or ending

address depending on the current data transfer mode. For

MSB-first format, the specified address is an ending address

or the most significant address in the current cycle. Remaining

internally by the serial port controller by decrementing from

the specified address. For LSB-first format, the specified address

is a beginning address or the least significant address in the

current cycle. Remaining register addresses for multiple byte

data transfers are generated internally by the serial port

controller by incrementing from the specified address.

MSB/LSB TRANSFERS

The serial port can support both MSB-first and LSB-first data

formats. This functionality is controlled by Register 0x00, Bit 6.

The default is Logic 0, which is MSB-first format.

When using MSB-first format (LSBFIRST = 0), the instruction

and data bit must be written from MSB to LSB. Multibyte data

transfers in MSB-first format start with an instruction byte that

includes the register address of the most significant data byte.

Subsequent data bytes are loaded into sequentially lower address

locations. In MSB-first mode, the serial port internal address

generator decrements for each byte of the multibyte data

transfer.

When using LSB-first format (LSBFIRST = 1), the instruction

and data bit must be written from LSB to MSB. Multibyte data

transfers in LSB-first format start with an instruction byte that

includes the register address of the least significant data byte.

Subsequent data bytes are loaded into sequentially higher

address locations. In LSB-first mode, the serial port internal

address generator increments for each byte of the multibyte

data transfer.

Use of a single-byte transfer when changing the serial port data

format is recommended to prevent unexpected device behavior.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

Chip Select Bar (CSB)

Active low input starts and gates a communication cycle. It

allows more than one device to be used on the same serial

communication lines. CSB must stay low during the entire

communication cycle. Incomplete data transfers are aborted

anytime the CSB pin goes high. SDO and SDIO pins go to a

high impedance state when this input is high.

Serial Clock (SCLK)

The serial clock pin is used to synchronize data to and from the

device and to run the internal state machines. The maximum

frequency of SCLK is 40 MHz. All data input is registered on

the rising edge of SCLK. All data is driven out on the falling

edge of SCLK.

Serial Port Data I/O (SDIO)

Data is always written into the device on this pin. However,

SDIO can also function as a bidirectional data output line. The

configuration of this pin is controlled by Register 0x00, Bit 7.

The default is Logic 0, which configures the SDIO pin as

unidirectional.

Serial Port Data Output (SDO)

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. The configuration of this

pin is controlled by Register 0x00, Bit 7. If this bit is set to a

Logic 1, the SDO pin does not output data and is set to a high

impedance state.

R/W N1 N0 A4 A3

A2 A1 A0 D7 D6N D5N

D00

D10

D20

D30

D7 D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Figure 52. Serial Register Interface Timing Diagram, MSB First

A0 A1 A2 A3 A4

N0 N1 R/W D00 D10 D20

D7N

D6N

D5N

D4N

D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Figure 53. Serial Register Interface Timing Diagram, LSB First

INSTRUCTION BIT 6

INSTRUCTION BIT 7

CSB

SCLK

SDIO

tDS

tDH

tPWH

tPWL

fSCLK–1

Figure 54. Timing Diagram for SPI Write Register

DATA BIT N – 1

DATA BIT N

CSB

SCLK

SDIO

SDO

tDV

Figure 55. Timing Diagram for SPI Read Register

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