MAX5500AGAP+ datasheet(3/14 Pages) MAXIM

3 / 14 page

Low-Power, Quad, 12-Bit

Voltage-Output DACs with Serial Interface

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(MAX5500 (VDD = +5V ±10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V ±10%, VREFAB = VREFCD = 1.5V), VAGND = VDGND = 0,

RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C. Output buffer connected in unity-

gain configuration (Figure 9).)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL OUTPUTS

Output High Voltage

VOH

ISOURCE = 2mA

VDD - 0.5

Output Low Voltage

VOL

ISINK = 2mA

0.13

0.4

DYNAMIC PERFORMANCE

Voltage Output Slew Rate

0.6

V/µs

To ±0.5 LSB, VSTEP = 2.5V

MAX5500A/MAX5500B

Output Settling Time

To ±0.5 LSB, VSTEP = 2.5V

MAX5501A/MAX5501B

µs

Output Voltage Swing

Rail-to-rail (Note 2)

0 to VDD

Current into FB_

0.1

µA

OUT_ Leakage Current in

Shutdown

RL =

∞

±0.01

±1.0

µA

MAX5500A/MAX5500B

Startup Time Exiting Shutdown

Mode

MAX5501A/MAX5501B

µs

Digital Feedthrough

CS =VDD, fIN = 100kHz

•s

Digital Crosstalk

5nV

•s

POWER SUPPLIES

MAX5500A/MAX5500B

4.5

5.5

Supply Voltage

VDD

MAX5501A/MAX5501B

3.0

3.6

Supply Current

IDD

(Note 3)

0.85

1.1

Supply Current in Shutdown

(Note 3)

µA

Reference Current in Shutdown

(Note 3)

µA

TIMING CHARACTERISTICS (Figure 6)

SCLK Clock Period

tCP

100

SCLK Pulse-Width High

tCH

SCLK Pulse-Width Low

tCL

CS Fall to SCLK Rise Setup

Time

tCSS

SCLK Rise to

CS Rise Hold

Time

tCSH

0ns

DIN Setup Time

tDS

DIN Hold Time

tDH

0ns

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